• Walter Schwarzenbach

     

    PhD.

    Soitec

     

     

    主題

     

    SmartSiCTM : Engineered SiC for high-voltage power applications

     

    講師簡介

     

    Walter Schwarzenbach (m) has received an Engineer Degree in Physics from the Swiss Federal Institute of Technology in Lausanne in 1994, and a PhD Degree in Physics from the University of Grenoble in 1999. He joined Soitec in 2000 as process development engineer then became project leader in charge of SmartCutTM process industrialization for several 300mm Partially-Depleted SOI substrate generations. From 2009 to 2018, he was in charge as Product Leader of Fully-Depleted SOI, Imager SOI and 2.5D - 3D materials definition and introduction. Since 2019, as part of the Innovation team, he is Technology Manager for SmartCut SiC engineered substrates, said SmartSiCTM. He is author or co-author of more than 50 articles in international refereed journals and conferences and more than 30 patents.

     

    演講大綱

     

    SmartSiC TM engineered substrates are proposed to answer the power device needs for high quality, ultra low resistivity materials. Smart Cut TM technology is applied to SiC material. It combines hydrogen implantation, conductive wafer bonding and high temperature finishing prior polishing to transfer an optimized high quality epi-ready 4H-mSiC layer on a ultra high conductivity handle material. 150mm substrates are already engaged in device qualification, while early 200mm substrates are available. Performance, including electrical and thermal material properties has been validated from room up to power device operating temperatures. Metrology adapted to the specific optical properties of the SmartSiC substrate has been developed. Since SmartCut technology replicate the crystal quality of the donor wafer, adapted DUV laser-inspection has also been demonstrated with hundreds of nanometer threshold.